`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2022/06/17 10:33:38
// Design Name: 
// Module Name: barrier_rol_shift32
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module barrier_rol_shift32(
    input [31:0] Din,
    input [4:0] Shf_num,
    output [31:0] Dout
    );
    wire [31:0] d0,d1,d2,d3;
    assign d0=(Shf_num[0]==0)?Din:{Din[30:0],Din[31]};
    assign d1=(Shf_num[1]==0)?d0:{d0[29:0],d0[31:30]};
    assign d2=(Shf_num[2]==0)?d1:{d1[27:0],d1[31:28]};
    assign d3=(Shf_num[3]==0)?d2:{d2[23:0],d2[31:24]};
    assign Dout=(Shf_num[4]==0)?d3:{d3[15:0],d3[31:16]};
endmodule

module barrier_rol_shift16(
    input [15:0] Din,
    input [3:0] Shf_num,
    output [15:0] Dout
    );
    wire [15:0] d0,d1,d2;
    assign d0=(Shf_num[0]==0)?Din:{Din[14:0],Din[15]};
    assign d1=(Shf_num[1]==0)?d0:{d0[13:0],d0[15:14]};
    assign d2=(Shf_num[2]==0)?d1:{d1[11:0],d1[15:12]};
    assign Dout=(Shf_num[3]==0)?d2:{d2[7:0],d2[15:8]};
endmodule

module barrier_ror_shift4(
    input [3:0] Din,
    input [1:0] Shf_num,
    output [3:0] Dout
    );
    wire [3:0] d0;
    assign d0=(Shf_num[0]==0)?Din:{Din[0],Din[3:1]};
    assign Dout=(Shf_num[1]==0)?d0:{d0[1:0],d0[3:2]};
endmodule

module barrier_rol_shift4(
    input [3:0] Din,
    input [1:0] Shf_num,
    output [3:0] Dout
    );
    wire [3:0] d0;
    assign d0=(Shf_num[0]==0)?Din:{Din[2:0],Din[3]};
    assign Dout=(Shf_num[1]==0)?d0:{d0[1:0],d0[3:2]};
endmodule

module rol_shift16B(input [16*8-1:0] Din,
    input [3:0] Shf_num,
    output [16*8-1:0] Dout
    );
    wire [16*8-1:0] d0,d1,d2;
    assign d0=(Shf_num[0]==0)?Din:{Din[15*8-1:0],Din[16*8-1:15*8]};
    assign d1=(Shf_num[1]==0)?d0:{d0[14*8-1:0],d0[16*8-1:14*8]};
    assign d2=(Shf_num[2]==0)?d1:{d1[12*8-1:0],d1[16*8-1:12*8]};
    assign Dout=(Shf_num[3]==0)?d2:{d2[8*8-1:0],d2[16*8-1:8*8]};
endmodule

module ror_shift16B(input [16*8-1:0] Din,
    input [3:0] Shf_num,
    output [16*8-1:0] Dout
    );
    wire [16*8-1:0] d0,d1,d2;
    assign d0=(Shf_num[0]==0)?Din:{Din[1*8-1:0],Din[16*8-1:1*8]};
    assign d1=(Shf_num[1]==0)?d0:{d0[2*8-1:0],d0[16*8-1:2*8]};
    assign d2=(Shf_num[2]==0)?d1:{d1[4*8-1:0],d1[16*8-1:4*8]};
    assign Dout=(Shf_num[3]==0)?d2:{d2[8*8-1:0],d2[16*8-1:8*8]};
endmodule

module lshift_128B(
    input [1023:0] din,
    input [6:0] shf_num,
    output [1023:0] dout);
    wire [1023:0] d0,d1,d2,d3,d4,d5;
    assign d0=(shf_num[0]==0)?din:{din[1015:0],8'b0};   //1 bute
    assign d1=(shf_num[1]==0)?d0:{d0[1007:0],16'b0};    //2 bytes
    assign d2=(shf_num[2]==0)?d1:{d1[991:0],32'b0};    //4 bytes
    assign d3=(shf_num[3]==0)?d2:{d2[959:0],64'b0};    //8 bytes
    assign d4=(shf_num[4]==0)?d3:{d3[895:0],128'b0};   //16 bytes
    assign d5=(shf_num[5]==0)?d4:{d4[767:0],256'b0};        //32 bytes
    assign dout=(shf_num[6]==0)?d5:{d5[511:0],512'b0};        //32 bytes
endmodule

module rshift_64B(input [511:0] din,
    input [5:0] shf_num,
    output [511:0] dout);
    wire [511:0] d0,d1,d2,d3,d4;
    assign d0=(shf_num[0]==1'b0)?din:{8'b0,din[511:8]};
    assign d1=(shf_num[1]==1'b0)?d0:{16'b0,d0[511:16]};
    assign d2=(shf_num[2]==1'b0)?d1:{32'b0,d1[511:32]};
    assign d3=(shf_num[3]==1'b0)?d2:{64'b0,d2[511:64]};
    assign d4=(shf_num[4]==1'b0)?d3:{128'b0,d3[511:128]};
    assign dout=(shf_num[5]==1'b0)?d4:{256'b0,d4[511:256]};
endmodule

